FPGA Engineer - Radar

About the role

Alta Ares, an air defense company building AI-guided interceptors against drones and cruise missiles, is looking for an FPGA Engineer in Paris. The role turns radar sensing requirements into FPGA designs that support reliable drone detection, working across RF, electronics and software teams.

Key responsibilities

• Define how radar data is acquired, processed and delivered to the rest of the system
• Set processing budgets and choose implementation approaches based on detection performance, latency, numerical accuracy and FPGA resources
• Build reference models of radar behaviour in noise and clutter and develop reusable RTL functions for waveform generation and receive processing in FMCW and pulsed radar
• Implement target extraction stages such as matched filtering, pulse compression, range-Doppler processing, clutter rejection and CFAR detection
• Integrate ADC/DAC interfaces, coordinate transmit and receive timing and synchronise with the radar front end
• Specify how detections and measurements are passed to tracking functions and embedded software
• Verify designs with automated testbenches and hardware-in-the-loop testing, and improve the processing chain using lab and field results
• Document design decisions, interfaces and validation results

Required profile

• At least three years of FPGA development experience, with practical exposure to radar or sonar processing
• Master's degree or equivalent in Electrical Engineering, Signal Processing, Applied Physics or a related field
• Ability to move a signal-processing function from algorithmic description to verified RTL in VHDL or Verilog/SystemVerilog
• Strong DSP foundations (FFT, digital filtering, windowing, quantization and fixed-point precision)
• Experience with testbenches, FPGA debugging and hardware-in-the-loop validation
• Methodical approach to debugging and documentation, clear communication, autonomy and high integrity with sensitive defence technologies

Required skills

• Radar processing: matched filtering, pulse compression, range-Doppler maps, CFAR, FMCW and pulsed radar
• RTL coding in VHDL or Verilog/SystemVerilog
• Understanding of how radar estimates range and velocity and distinguishes returns from clutter