Internship - FPGA Hardware Design (PQ Cryptography Accelerator)

About the role

CryptoNext Security is a deep-tech startup building post-quantum cryptography solutions for finance, defence and telecommunications. As part of an exploratory project on hardware accelerators for post-quantum cryptography (PQC), it is looking for a highly motivated FPGA Hardware Design Engineer to take ownership of a key strategic project combining hardware/software codesign (FPGA development and low-level C) and PQC accelerators. The internship runs for 6 months, from December 2026 to June 2027.

Key responsibilities

• Study state-of-the-art approaches to PQC hardware acceleration in the scientific literature and implement the selected ones.
• Focus on the Number Theoretic Transform (NTT) and the Keccak state permutation, key functions in ML-KEM and ML-DSA algorithms.
• Develop system-level RTL code in SystemVerilog and integrate the accelerators into a complete hardware/software system.
• Evaluate the impact of the accelerators on application-level performance on an AMD Xilinx ZCU104 board (Zynq UltraScale+ MPSoC).
• Demonstrate that a hardware accelerator for the NTT or Keccak permutation can speed up the corresponding ML-KEM or ML-DSA implementation in the CryptoNext Quantum Safe Library (C-QSL).

Required profile

• Final-year engineering student or M2 / Master's degree in computer engineering, electrical engineering, embedded systems, microelectronics or a related field.
• Strong interest in hardware/software codesign and embedded systems; ability to work independently, investigate technical problems and communicate results clearly.

Required skills

• FPGA development and RTL design in Verilog, SystemVerilog or VHDL.
• Experience with AMD Vivado or Intel Altera Quartus.
• Good C programming under Linux, with basic assembly knowledge.
• Git and standard software development workflows; shell scripting, Makefiles and compiler toolchains.
• Profiling and debugging tools.
• Nice to have: AMBA protocols (AXI, AHB, APB, CHI), JTAG debugging, QEMU (including the Xilinx fork), QEMU/SystemC/Verilator co-simulation, and prior exposure to PQC, lattice-based cryptography, ML-KEM, ML-DSA, NTT, DFT or Keccak.