Senior Integration & Yield Engineer – Superconducting Quantum Circuits

About the role

We are looking for a Senior Integration & Yield Engineer to join the Foundries & Process Integration team within the Quantum Hardware & Infrastructure department. The role bridges qubit design and chip manufacturing, ensuring designs translate into high‑performing fabricated circuits and providing data for process improvements.

Key responsibilities

• Own yield monitoring across fabrication flows, define metrics, build automated dashboards and provide real‑time visibility of fab performance.
• Lead root‑cause analysis of systematic and random yield detractors, using advanced statistical methods (Python, JMP) and SPC/DOE techniques.
• Define and maintain robust integration flows, establish Design for Manufacturability (DFM) guidelines, and document reference fabrication processes.
• Maintain lookup tables linking design parameters to Josephson junction fabrication and develop Python tools to automate the design‑to‑wafer pipeline.
• Coordinate failure analysis at room and cryogenic temperatures, using electrical test data, inline metrology and microscopy (SEM, AFM), and drive corrective actions with structured problem‑solving methods.

Required profile

• Master’s degree or Ph.D. in Physics, Materials Science or a related field.
• At least 3 years of hands‑on experience in semiconductor or superconducting circuit nanofabrication or process integration.
• Proven expertise in yield engineering, statistical process control, design of experiments and data analysis.
• Strong communication skills and ability to work in a cross‑disciplinary environment.

Required skills

• Python scripting for data analysis and workflow automation.
• Statistical analysis tools (JMP, SPC, DOE).
• Root‑cause analysis methodologies (5 Whys, Ishikawa, FMEA).
• Microscopy techniques (SEM, AFM) and cryogenic testing knowledge.