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This job expired on 25/08/2026. It no longer accepts applications.

Prototyping Design Software Engineer

SPECS · Ville de Paris

🇬🇧 English
FPGA HAPS ZeBu FSBL embedded software device drivers RTOS eMMC LPDDR PCIe UART QSPI Flash SPI I2C I3C GPIO JTAG waveform analysis

Job description

About the role

Specs Inc., a Snap Inc. subsidiary focused on advanced AR eyewear, is seeking a Prototyping Design Engineer to accelerate early platform bring‑up. You will translate complex SoC RTL into FPGA, HAPS, and ZeBu prototypes, enabling firmware development and hardware validation.

Key responsibilities

  • Port SoC and subsystem RTL onto FPGA, HAPS, and ZeBu platforms while preserving ASIC‑level behavior.
  • Build and maintain pre‑silicon platforms for bootloader/FSBL bring‑up and early firmware development.
  • Adapt RTL wrappers and platform‑specific logic for HAPS/ZeBu interface PHY changes.
  • Develop and integrate low‑level embedded software, including board support packages, device drivers, and diagnostics.
  • Debug complex hardware/software bring‑up issues across all prototyping targets.
  • Design and execute pre‑tapeout SoC validation tests using firmware, bare‑metal, and RTOS‑based applications.
  • Collaborate with RTL, verification, system software, and infrastructure teams.

Required profile

  • Strong experience in SoC prototyping and hardware bring‑up.
  • Hands‑on expertise with FPGA, HAPS, and ZeBu platforms.
  • Solid understanding of boot processes, FSBL, and embedded software development.
  • Ability to work across hardware integration, low‑level software debug, and RTOS/bare‑metal environments.

Required skills

  • SoC RTL prototyping
  • FPGA, HAPS, ZeBu platforms
  • Bootloader/FSBL development
  • Embedded software (board support code, device drivers)
  • RTOS and bare‑metal programming
  • Hardware interfaces: eMMC, LPDDR, PCIe, MIPI CSI‑2, MIPI DSI, UART, QSPI Flash, SPI, I2C, I3C, GPIO, JTAG
  • Debug tools: JTAG/SWD, waveform analysis, timing‑report review
  • Memory‑model integration, reset and clock sequencing, controller/PHY interaction

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Published 3 months ago

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SPECS

Ville de Paris