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Layout Scale-Up Engineer

alice-bob · Paris

New
🇬🇧 English
Python gdstk gdsfactory KLayout API SKILL Tcl Cadence Siemens Synopsys Calibre xRC Quantus StarRC FastCap FastHenry DRC LVS PEX GDSII OASIS

Job description

About the role

Alice & Bob is building a fault‑tolerant quantum computer based on superconducting cat qubits. This role creates the layout infrastructure—PDK, generators, automated flows—that enables chip complexity to grow from hundreds to millions of qubits while keeping design cycle time flat.

Key responsibilities

  • Build and own the PDK, including layer stack, technology files, parametric cells and DRC/LVS decks.
  • Design a tile‑based, hierarchical layout methodology for reticle‑compatible, wafer‑scale and multi‑chip designs.
  • Write and maintain layout generators (Python/GDS or vendor EDA scripting) that produce DRC‑clean GDSII/OASIS from architecture specifications.
  • Own end‑to‑end mask generation: floorplan → hierarchical layout → DRC/LVS/PEX sign‑off → wafer map and tape‑out package.
  • Drive automation targets (>50% automated layout at 400 qubits, >80% at 1,000, >90% at 10,000).
  • Keep DRC/LVS/PEX runtime and file size tractable for designs with up to 10⁸ elements.
  • Evaluate and deploy the EDA toolchain (Cadence/Siemens/Synopsys or open‑source) and integrate with EM‑simulation handoff.
  • Serve as physical‑implementation sign‑off at design review gates before mask release.

Required profile

  • 5+ years in physical design, custom/analog layout, PDK development, or mask data preparation in a semiconductor context, with at least one production tape‑out owned end‑to‑end.
  • Proven experience scaling a layout methodology from hand‑drawn to generator‑driven, hierarchical flows.
  • Hands‑on parasitic extraction experience with commercial (Calibre xRC/xACT, Quantus, StarRC) and/or field‑solver tools (FastCap, FastHenry, BEM/FEM).
  • Strong automation scripting skills in Python (gdstk, gdsfactory, KLayout API) and vendor languages (SKILL, Tcl).
  • Fluent in DRC/LVS deck authoring, GDSII/OASIS, reticle and stepper constraints, and tape‑out data preparation.
  • Ability to translate frequency plans or floorplan constraints into geometry.
  • Fluent English with excellent written and verbal communication.

Required skills

  • Python (gdstk, gdsfactory, KLayout API)
  • Vendor scripting languages (SKILL, Tcl)
  • EDA toolchains (Cadence, Siemens, Synopsys)
  • Parasitic extraction tools (Calibre xRC/xACT, Quantus, StarRC, FastCap, FastHenry)
  • DRC/LVS/PEX deck authoring and verification
  • GDSII/OASIS file handling and mask data preparation

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Source : ats:lever

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Published 3 hours ago

Expires 1 month from now

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alice-bob

Paris