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3D Integration Engineer

c12qe · Paris

New
60,000 - 78,000 EUR/year 🇬🇧 English
3D integration micro-bumps hybrid bonding redistribution layers chiplet interfaces wafer bonding flip-chip assembly thin-film deposition lithography etching electroplating CMP CAD electromagnetic simulation multiphysics simulation statistical analysis semiconductor process-development tools

Job description

About the role

C12 Quantum Electronics is looking for a 3D Integration Engineer to develop advanced packaging and heterogeneous‑integration technologies for scalable quantum‑computing hardware. You will design and optimise interconnects between quantum devices, control electronics, photonic components and cryogenic systems while ensuring signal integrity, thermal performance and reliability.

Key responsibilities

  • Develop 2.5D and 3D integration architectures for quantum processors and supporting electronics.
  • Design interposers, through‑silicon vias, micro‑bumps, hybrid bonds, redistribution layers and chiplet interfaces.
  • Integrate QPUs with cryogenic CMOS, RF/microwave circuitry, photonics, MEMS and packaging substrates.
  • Perform electrical, electromagnetic, mechanical and thermal simulations.
  • Define fabrication flows and design rules with foundries, packaging partners and internal teams.
  • Develop test vehicles, conduct experimental measurements, analyse data and improve yield.
  • Document designs, process specifications, qualification results and technology roadmaps.
  • Collaborate with quantum‑device, circuit‑design, cryogenic, materials, manufacturing and systems teams.

Required profile

  • Bachelor’s or Master’s degree in electrical engineering, materials science, mechanical engineering, applied physics or related discipline.
  • Experience in semiconductor packaging, wafer‑level integration, MEMS, micro‑fabrication or heterogeneous integration.
  • Familiarity with processes such as wafer bonding, hybrid bonding, TSVs, flip‑chip assembly, thin‑film deposition, lithography, etching, electroplating or CMP.
  • Knowledge of package‑level electrical, thermal and mechanical design.
  • Strong experimental, troubleshooting, documentation and cross‑functional communication skills.

Required skills

  • 2.5D and 3D integration design
  • Interposer and TSV design
  • Hybrid bonding, micro‑bump and redistribution layer technologies
  • Wafer bonding, flip‑chip assembly, thin‑film deposition, lithography, etching, electroplating, CMP
  • CAD tools and electromagnetic/multiphysics simulation software
  • Statistical analysis and semiconductor process‑development tools

What we offer

  • Base salary €60,000 – €78,000 per year
  • Stock options (BSPCE/ESOP) for every employee
  • Sponsored trips to conferences worldwide
  • Swile meal vouchers and mental‑health support (moka.care)
  • Training budget / annual learning & development allowance
  • Sabbatical leave after two years
  • Vibrant office culture with two Paris locations, team lunches, off‑site events and Friday breakfasts

Questions fréquentes

Le salaire proposé pour ce poste est de 60-78k EUR par an. Le détail figure dans l'annonce.
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Source : ats:lever

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Published 14 hours ago

Expires 1 month from now

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c12qe

Paris