Lead Debug/Trace/Profiling Design Engineer

About the role

SiFive is looking for a technical lead to design industry‑leading debug, trace and profiling IP for its RISC‑V processor cores. The role will drive the creation of highly configurable hardware generators and collaborate with architecture, performance, software and hardware teams.

Key responsibilities

• Architect, design and implement debug, trace and profiling hardware as configurable RTL generators.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and improve automatic configuration, documentation and verification flows.
• Collaborate with customers, partners and RISC‑V International to shape future debug and profiling solutions.
• Perform sandbox verification and work with the verification team to develop thorough test plans.

Required profile

• 7+ years of industry experience leading architecture, micro‑architecture and RTL design for debug/trace/profiling hardware.
• MS/PhD in EE, CE, CS or related technical discipline.
• Ability to work in a fast‑paced, dynamic environment and share knowledge through documentation.

Required skills

• Debug, trace and profiling concepts, JTAG and cJTAG interfaces.
• CPU architectures, power management and SoC design.
• Hardware design in Verilog, SystemVerilog or VHDL.
• Chisel/Scala, RISC‑V architecture, Git, Jira, Confluence (plus any object‑oriented or functional programming language).