Digital Backend Design Engineer – Full‑Chip Physical Implementation

About the role

Arago is seeking a Digital Backend Design Engineer to lead the physical implementation of digital ICs from RTL to GDSII. You will work with cutting‑edge EDA tools to deliver high‑performance, low‑power, and area‑efficient silicon while meeting strict timing and yield goals.

Key responsibilities

• Perform full‑chip and block‑level physical design tasks such as floorplanning, placement, clock‑tree synthesis, routing, and physical verification.
• Develop and optimise the digital backend flow, including automation with Tcl scripts.
• Drive timing closure, power optimisation, and ensure DRC/LVS/ERC compliance.
• Collaborate with RTL, DFT and packaging teams to resolve timing and interface issues.
• Support tape‑out preparation and final sign‑off processes.

Required profile

• Master’s or PhD in Electrical/Electronic Engineering or a related field.
• 4+ years of experience in digital IC backend implementation.
• Proficiency in English; French is a plus.

Required skills

• Cadence Innovus
• Cadence Genus
• Tcl scripting for flow automation
• Place & route (P&R) expertise
• Static timing analysis (STA)
• DRC/LVS verification
• IR‑drop and electromigration (EM) analysis
• Experience with advanced technology nodes (22 nm or below)

What we offer

• Competitive cash compensation based on location and experience.
• Early‑stage stock option plan.
• Relocation bonus and moving expense coverage for nearby moves.
• Comprehensive healthcare coverage, family‑friendly options, and pension contributions.