Senior Mixed-Signal Verification Engineer

About the role

Arago is looking for a Senior Mixed‑Signal Verification Engineer to lead the verification of digital‑to‑analog interfaces on its cutting‑edge System‑on‑Chip products. You will work in a fast‑paced environment alongside analog, RTL, architecture and firmware teams to ensure seamless integration and drive verification to sign‑off.

Key responsibilities

• Define and own the mixed‑signal verification methodology and verification plan for digital‑to‑analog blocks.
• Build and maintain verification environments at block, subsystem and SoC levels.
• Create tests, assertions, checkers, scoreboards and functional coverage models.
• Verify digital control and configuration of analog/mixed‑signal circuitry across normal operation, corner cases and error conditions.
• Run regressions, analyse coverage, debug failures and push verification to sign‑off.
• Develop or integrate behavioral and real‑number models for efficient mixed‑signal simulation.
• Collaborate closely with analog, RTL, architecture, firmware and SoC verification teams to resolve interface issues.

Required profile

• Strong hands‑on experience in ASIC or SoC verification.
• Proven experience verifying mixed‑signal blocks or digital‑to‑analog and analog‑to‑digital interfaces.
• Deep knowledge of SystemVerilog and practical use of UVM or equivalent methodology.
• Solid debugging skills across RTL, clocks, resets, configuration and analog behavior.
• Proficiency in scripting/automation languages such as Python, Tcl or shell.
• Professional proficiency in English.

Required skills

• ASIC verification
• SoC verification
• Mixed‑signal verification
• Digital‑to‑analog and analog‑to‑digital interface testing
• SystemVerilog
• UVM (or equivalent verification methodology)
• Testbench development, assertions, scoreboards, functional coverage
• Debugging RTL and analog behavior
• Scripting/automation (Python, Tcl, shell)