Digital Verification Engineer

About the role

We are looking for a Digital Verification Engineer to ensure the functional integrity, performance and reliability of next‑generation optical chips. You will work closely with architects, designers and customers to translate logic requirements into robust verification strategies.

Key responsibilities

• Develop and execute verification plans for complex digital and mixed‑signal optical chip designs.
• Create and maintain scalable UVM‑based testbenches, agents, monitors and scoreboards.
• Perform netlist‑level simulations with SDF back‑annotation for timing‑accurate verification.
• Support FPGA/ASIC bring‑up and post‑silicon validation as needed.
• Collaborate with cross‑functional teams to provide clear feedback and achieve functional coverage closure.

Required profile

• Bachelor’s, Master’s or PhD in Electrical/Computer Engineering or a related field.
• Hands‑on experience with SystemVerilog and the UVM verification methodology.
• Familiarity with standard high‑speed protocols such as AXI/AXI‑Stream, APB/AHB, I2C, JTAG and PCIe.
• Experience verifying RISC‑V or equivalent processor architectures in an ASIC context.
• Strong analytical and communication skills; fluent English (French a plus).

Required skills

• SystemVerilog
• UVM framework
• AXI, AXI‑Stream, APB, AHB, I2C, JTAG, PCIe protocols
• RISC‑V CPU verification
• FPGA/ASIC bring‑up
• SDF back‑annotation
• Constrained random testing, assertions, transaction‑level modeling
• Coverage‑driven verification and regression automation