Senior SOC Design For Test Engineer

About the role

NXP Semiconductors is looking for an experienced Senior Design‑For‑Test (DFT) Engineer to join its AI and Chip Engineering (ACE) team in Grenoble. You will create and verify advanced DFT architectures for complex SoC products used in automotive and industrial applications.

Key responsibilities

• Define and implement digital DFT solutions (Scan, ATPG, Memory BIST, Logic BIST, JTAG) at IP, subsystem and SoC levels.
• Develop and run ATPG patterns to meet fault‑coverage targets for stuck‑at, transition‑delay, and memory testing.
• Perform DFT verification, simulation and validation to ensure testability.
• Collaborate with design, verification, physical design and product engineering teams throughout the development cycle.
• Support silicon bring‑up, post‑silicon debug and analysis of test results to improve yield.
• Work with manufacturing and ATE teams to enable efficient production test flows.
• Evaluate and adopt new DFT methodologies, tools and AI‑driven techniques.

Required profile

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics or related field.
• Strong experience in DFT design and verification for complex ASIC or SoC products.
• Hands‑on experience with silicon bring‑up and post‑silicon debug preferred.
• Excellent analytical, problem‑solving and communication skills.

Required skills

• DFT methodologies: Scan design, ATPG, Memory BIST, Logic BIST, JTAG/Boundary Scan.
• Industry‑standard DFT tools: Synopsys TestMAX, Cadence Modus, Siemens Tessent.
• Hardware description languages: Verilog, SystemVerilog.
• Scripting/programming: TCL, Python, Perl.