Senior ASIC Architect

About the role

Arago is seeking a Senior ASIC Architect to lead the definition and realization of next‑generation compute architectures. You will drive system‑level design, guide cross‑functional engineering teams, and shepherd silicon from concept through production.

Key responsibilities

• Own the top‑level architecture of Arago’s multiphysics compute platform, covering processing elements, interconnects, memory subsystems, and system‑level control.
• Define the architectural vision from concept through tape‑out, handling system modeling, specifications, and hand‑off to engineering teams.
• Mentor and coordinate hardware teams across RTL design, functional verification, and physical integration to ensure consistent technical direction.
• Collaborate with software, packaging, and system integration groups to guarantee scalability, performance, and reliability.
• Evaluate new architectural directions, build performance and cost models, and lead prototyping to de‑risk future innovations.

Required profile

• Proven track record designing complex, high‑performance digital systems such as multicore processors, vector engines, or domain‑specific accelerators.
• Deep expertise in computer architecture, memory hierarchies, interconnects, cache coherence, and instruction‑set design.
• Hands‑on experience with compute‑intensive blocks (vector ALUs, SIMD pipelines, systolic arrays, custom datapaths).
• Experience leading full ASIC development cycles from concept to tape‑out, including RTL, verification, and physical design.
• Familiarity with advanced integration technologies like HBM, chiplets, and 2.5D/3D packaging.

Required skills

• Computer architecture
• Memory hierarchy design
• Interconnect design
• Cache coherence protocols
• Instruction set design
• Performance‑power‑area trade‑off analysis
• Vector ALU and SIMD pipeline design
• Systolic array and custom datapath design
• ASIC development cycle management
• RTL implementation
• Functional verification
• Physical design and tape‑out
• HBM integration
• Chiplet integration
• 2.5D/3D integration technologies