Mixed‑Signal IC Design Engineer – High‑Performance Digital Subsystems

About the role

Arago is seeking a Mixed‑Signal IC Design Engineer to create high‑performance digital subsystems for mixed‑signal integrated circuits. You will own the full digital flow from RTL coding to physical implementation and tape‑out, working in a fast‑paced AI‑hardware environment.

Key responsibilities

• Design and verify digital blocks that interface with high‑speed analog circuits, including calibration engines, control FSMs, data converters and multiplexing logic.
• Integrate and customize external IP such as GPIOs, LVDS I/Os and serial interfaces while meeting analog timing constraints.
• Lead the digital implementation flow (RTL, synthesis, floorplanning, place‑and‑route, timing closure, sign‑off and tape‑out) for mixed‑signal modules.
• Collaborate with analog, layout and system teams to co‑optimize digital‑analog boundaries and resolve cross‑domain issues.
• Contribute to high‑speed serial I/O subsystems; experience with SerDes design is a strong advantage.

Required profile

• Proficient English communication; French is a plus.
• Strong background in digital RTL design for mixed‑signal environments.

Required skills

• Verilog / SystemVerilog RTL design.
• Digital‑analog integration expertise (timing closure, noise coupling, clock domain crossing, analog‑aware floorplanning).
• Design flow management from synthesis to tape‑out for analog/RF ICs.
• IP integration experience (GPIO, LVDS, SPI, I²C).
• High‑speed serial interface design, particularly SerDes.